Nonvolatile semiconductor memory devices are well-known in the art. These devices include the erasable-programmable read-only memory (EPROM), the electrically-erasable-programmable read-only memory (EEPROM), and most recently, the flash memory. Flash memories are widely used for nonvolatile memory applications because they combine several of the most desirable characteristics of EPROMs and EEPROMs, including electrical erasability and erasability on a global or sector basis.
FIG. 1 is a block diagram of a flash memory 110. This block diagram is also representative of the architecture of other types of memories. The flash memory 110 includes a memory array 112, and address row decoder 114, a control circuit 116, an input/output (I/O) data circuit 118 and a column I/O circuitry 120. Memory 110 operates in response to external signals provided by a controlling device 122, such as a microprocessor.
The principle of operation of flash memories, such as memory 110, is well known and therefore is only briefly described herein. Controller 122 initiates a memory operation by asserting chip enables 101 and supplying address signals A.sub.0 -A.sub.N (corresponding to 2.sup.N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write or program operation, controller 122 supplies the data to be written to the addressed memory location via the bi-directional input/output lines I/O.sub.O -I/O.sub.K (corresponding to a K+1 bit wide memory word). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bi-directional input/output lines I/O.sub.O -I/O.sub.K. Memory 110 also provides connections for external power supply (V.sub.cc) and ground (GND) signals.
The heart of memory 110 is memory array 112, which consists of flash memory cells, each capable of storing one bit of data, arranges in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a program) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
The memory array 112 may be organized in sectors, each sector consisting of a plurality of rows of memory cells. During an erase operation, the memory cells in a selected sector are simultaneously erased.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via bit lines BL.sub.O -BL.sub.K. When the memory operation is a read, bit lines BL.sub.O -BL.sub.K are coupled to sense amplifiers in the column I/O 120 that "sense" the data stored in the corresponding cells of the row whose word line WL is enabled. When the memory operation is a program operation, the bit lines BL.sub.O -BL.sub.K carry the signals used to program the corresponding cells of the row associated with the enabled word line.
Control circuit 116 controls the other blocks of memory 110 when a chip enable signal 101 enables operation of the memory. Depending on the operation to be performed, the control circuit issues the appropriate control signals 117a and 117b to row decoder 114 and I/O data circuit 118, respectively.
Regardless of whether the memory operation is a read or program, row decoder 114 decodes the address signals A.sub.O -A.sub.N and activates the word line WL of the row that includes the memory word that is the target of the current memory operation. If the operation is a program, I/O data circuitry 118 buffers input data signals I/O.sub.O -I/O.sub.K and outputs the buffered data to column I/O 120 via bi-directional data bus 119. Column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL.sub.O -BL.sub.K. The signals on the bit lines BL.sub.O -BL.sub.K are used to program the cells composing the word whose word line was activated for the current operation by row decoder 114.
If the operation is a read, sense amplifiers in column I/O 120 sense the signals on the respective bit lines BL.sub.O -BL.sub.K, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via bi-directional bus 119. The output data are buffered by I/O data circuit 118 and latched onto bi-directional data lines I/O.sub.O -I/O.sub.K for use by controller 122.
For proper operation of the memory cells in flash memory 110, row decoder 114 must provide the enabled word line WL with a voltage appropriate for the selected read, program or erase operation. For example, for conventional flash memory cells the enabled word line WL must typically reach a voltage of 4-5 volts (V) during a read operation to provide the memory cells with a sufficient read operation margin. The memory cells of some other types of nonvolatile memories, such as EPROMs, typically have similar word line voltage requirements.
Memory 110 may use a low-voltage power supply (V.sub.cc) of less than 4-5 V. Such low-voltage power supply memories, in which V.sub.cc may be as low as about 1.8 V, are increasing in popularity as battery-powered applications become more widespread. In these memories, a voltage higher than V.sub.cc is necessary to drive the word lines to the required 4-5 V.
One technique used to drive the word lines to the required higher-than-Vcc voltage couples a bootstrap circuit to one or more inputs of row decoder 114. The bootstrap circuit is a well-known circuit used to generate a signal having a peak voltage higher than V.sub.cc. The bootstrap circuit outputs a fixed amount of charge via a bootstrap capacitance C.sub.boot. The voltage produced at the output of the bootstrap circuit is highly dependent on the load presented by the row decoder, decoder load capacitance C.sub.D, to the bootstrap circuit. Decoder load capacitance C.sub.D primarily consists of the gate and parasitic capacitances of the transistors in row decoder 114 connected to the bootstrap circuit. If the decoder load capacitance C.sub.D is relatively large compared to the size of the bootstrap capacitance C.sub.boot, the bootstrap circuit may be unable to generate the voltage necessary to drive the word lines.
To compensate for a relatively large decoder load capacitance C.sub.D, the size of the bootstrap capacitance C.sub.boot may be increased. However, a large bootstrap capacitance is undesirable for several reasons. First, the large bootstrap capacitance increases the size of the bootstrap circuit. Second, it increases the amount of noise generated by the bootstrap circuit. Third, it increases the power consumed by the bootstrap circuit. Therefore, for a memory 110 having a low-voltage power supply, it is important for row decoder 114 to minimize the decoder load capacitance C.sub.D presented to the bootstrap circuit.
In view of the foregoing, it is an object of the present invention to provide a row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry.